| Abstract: | 無線通訊發展至今, 使用多輸入多輸出(MIMO)結合正交分頻多工技術(OFDM)的無線通訊系統是當前通訊發展的主流趨勢, 而MIMO 系統中的預編碼技術是本篇論文所探討的重點。在實際系統中, 利用適當的挑選法則(selection criterion) 從編碼簿(codebook) 中挑選出最佳的碼字(codeword) 當作預編碼矩陣(precoding matrix), 回傳至傳送端以提升MIMO 系統傳輸的可靠度。本論文所使用的編碼簿為3GPP LTE Release 13所提出的下行鏈路(physical downlink shared channel) 編碼簿。隨著MIMO 所使用的天線數不斷的增加, 相應的編碼簿的碼字數目也越來越多, 使得挑選法則所需計算的數量越趨龐大, 因此我們針對了八根傳送天線的編碼簿提出了一種算法有效降低挑選法則所需的計算量, 進而減少預編碼系統的硬體運算複雜度。在硬體實作上, 我們使用Xilinx ISE 14.7來撰寫Verilog HDL code 以完成系統的暫存器傳輸級(register-transfer level, RTL) 模型, 並搭配使用Matlab 驗證RTL 模型的功能正確性, 最後再使用CIC 提供的Synopsys Design Compiler並採用TSMC90nm CMOS 製程來進行ASIC (application-specific integrated circuit) 電路合成。
The multiple input multiple output (MIMO) technique combined together with the orthogonal frequency division multiplexing (OFDM) is the mainstream of current wireless communication system. Among the various MIMO techniques, the precoding with limited feedback is the focus of this thesis. In the practical communication system, the optimal codeword is selected by the receiver from a finite-sized codebook following an appropriate selection criterion. The selected codeword is then sent back to the transmitter side. Next, the transmitter sends out precoded signals to improve the transmission reliability. The codebook considered in this paper is the physical downlink shared channel codebook adopted by the 3GPP LTE Release 13. Generally, as the number of transmitted antennas increases, the number of codewords in the corresponding codebook increases, resulting in a more complex codeword selection algorithm. In this thesis, we propose an algorithm for effectively reducing the computational complexity of the codeword selection for the transmitter with 8 antennas. We also propose a low cost hardware architecture for implementing our proposed algorithm. We compile our Verilog HDL code in the Xilinx ISE 14.7 environment to generate the register-transfer level (RTL) model for our proposed architecture. The RTL model is synthesized by the Synopsys Design Compiler to generate Application Specific Integrated Circuit (ASIC) under the TSMC 90nm CMOS process. |
