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    Please use this identifier to cite or link to this item: http://ccur.lib.ccu.edu.tw/handle/A095B0000Q/784

    Title: 可調整的硬體設計與實現應用於格拉姆矩陣之反矩陣運算;Scalable Hardware Design and Implementation for Matrix Inversion of Gramian Matrices
    Authors: 吳宜展;WU, YI-ZHAN
    Contributors: 通訊工程研究所
    Keywords: 大量天線;可調整式硬體;格拉姆矩陣;反矩陣;LDL分解;Large Antenna System;Scalable Hardware;Gramian Matrix;Matrix Inversion;LDL decomposition
    Date: 2017
    Issue Date: 2019-07-17 10:47:50 (UTC+8)
    Publisher: 通訊工程研究所
    Abstract: 近年來無線通訊開始往大量天線系統(large antenna system, LAS) 的研究與發展, 當然這其中有些困難與需要突破之處, 例如: 由於大量天線的關係, 會使得矩陣的大小較大的情況, 在處理方面較為麻煩, 而其中在檢測器(detector) 方面,像是zero-forcing 、MMSE(mininmum mean square error) detectors 中, 會需要處理格拉姆矩陣(Gramian Matrix) 的反矩陣運算, 本論文對於反矩陣運算進行硬體設計, 並且有規律的在增加維度的情況下硬體要如何增加設計, 以應用在不同維度下的反矩陣運算達到可調整(scalable) 的硬體設計, 而反矩陣的運算是透過LDL分解減少反矩陣運算的複雜度, 在硬體設計方面, 總共分為三部分, 一是計算LDL分解的L 、D矩陣, 二是計算L反矩陣, 最後運算所要計算的反矩陣, 透過運算完所需要的值更新後面的值的設計, 來達到在每次運算下的最大複雜度相同, 所以增加維度時, 硬體方面只需要增加一塊相同的運算單元(process element, PE) 即可, 以達到硬體方面上的可調整性, 最後在硬體實現上, 使用Xinlinx ISE 14.7進行VerilogHDL 撰寫以及RTL 上的驗證, 以及使用內建的驗證軟體來觀察輸入與輸出的正確性, 然後再使用CIC 的工作站用Synopsys Design Compiler 進行gate-level 的電路合成。
    In recent years, research and development of the wireless communication systemhas evolves to the scenario of large antennas, or the large antenna system (LAS). One difficulty for implementing such system is the processing of the matrices with large size. For example, the well-known zero-forcing (ZF) and minimum mean square error (MMSE) detectors require the computation of Grammian matrices of size equal to the number of transmit antennas. In this thesis, the scalable hardware design for matrix inversion of matrices of various sizes is studied. To compute the matrix inversion of Grammian matrices, computationally efficient LDL decomposition is applied at the algorithmic level. The algorithm is mapped to produce our proposed hardware design, which is comprised of three blocks: the block for calculating the L-matrix and D-matrix from the LDL decomposition, the block for calculating the matrix inverse of the L- matrix, and the block for calculating the matrix inverse. To obtain a design for scalable hardware architecture, our proposed architecture can compute the matrix inverse of a larger matrix if additional processing elements are added. Through the operation of the required value at the same time update the value in design to achieve the same maximum complexity in each operation. The proposed design is described by Verilog HDL and synthesized by Synopsys Design Compiler. Further implementation results are reported in the thesis.
    Appears in Collections:[通訊工程研究所] 學位論文

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