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    Please use this identifier to cite or link to this item: http://ccur.lib.ccu.edu.tw/handle/A095B0000Q/782


    Title: 硬體效能改善具有最大概似增強功能之平行化多棵樹軟式輸出檢測器;Hardware Improvement for the Soft-Output MIMO Detection with Parallel Tree Traversals and ML Enhancement
    Authors: 柯奕光;KO, YI-KUANG
    Contributors: 通訊工程研究所
    Keywords: 多輸入多輸出;空間多工;QR分解;層狀正交晶格偵測器;樹狀搜尋;軟性輸出檢測器;對數相似比;最大概似增強;Design Compiler;SOC Encounter;MIMO;SDM;QR decomposition;LORD;Tree search;Soft-output detector;Log likelihood ratio;ML enhancement;Design Compiler;SOC encounter
    Date: 2017
    Issue Date: 2019-07-17 10:47:49 (UTC+8)
    Publisher: 通訊工程研究所
    Abstract: 自從多天線多輸入多輸出 (Multiple Input Multiple Output, MIMO) 技術發展成熟,以及對於 throughput rate 的需求越來越高,也相對的讓天線增多和調變方式的密度提高,使得接收機端的檢測器越來越複雜。而在檢測器當中必須先進行前置處理,將通道矩陣進行 QR 分解 (QR Decomposition) ,方便檢測器來還原訊號;另外,檢測器可以分為2種類型:硬式輸出檢測 (Hard-Output) 以及軟式輸出檢測 (Soft-Output) ,而軟式輸出檢測的複雜度稍微高了一些,但卻可以提供給解碼器對數相似比 (Log Likelihood Ratio, LLR) 的資訊,進而使得在相同系統條件下,達到較低的錯誤率,也就是說系統效能會比較好。本論文考慮在 4×4 的空間多工 (Space Division Multiplexing, SDM) MIMO 系統下,調變方式使用 64 QAM。前置處理為 LORD (Layered ORthogonal lattice Detector) 演算法,並且為了方便時序的控制,在輸入通道矩陣與單位矩陣時兩者之間多空下一個 Clock cycle ,然後產生平行化多棵樹的 Q 和 R 矩陣提供給檢測器。檢測器使用 ORVD (Orthogonal Real Value Decomposition) 將複數訊號模型轉換成實數訊號模型,使得 R 矩陣具有平行處理的特性,加快處理的時間。在樹狀搜尋方式使用 LUT (Lookup Table) Modified FSD (Fixed Sphere Decoder) 演算法,此種方式只在實數訊號模型的最上面2層用 LUT 來選擇要展開的星座點,其他層則是只找最接近點,來降低系統的複雜度,並且因為使用了 LORD 演算法以及 multiple bit flipping,使得在計算 LLR 數值時不會有 bit vacancy 的問題產生。在後端 bit LLR 計算使用 ML enhancement 的方式,進一步降低錯誤率來提升系統的效能。在硬體實現的部分,我們使用 TSMC 90nm CMOS 製程並且以 Synopsys Design Compiler 進行合成 (Synthesis) , Cadence SOC Encounter 進行佈局繞線 (Place & Route) ,最大操作頻率為 250MHz ,吞吐量 (throughput) 可以達到 1Gbps。
    As the multiple input multiple output (MIMO) techniques develop, the use of large number of antennas and high modulation schemes is able provide high throughput-rate data communication. In the meantime, the computational complexity for the MIMO detector, especially the nearly optimal tree search detectors, also grows. The tree search MIMO detectors are divided into two categories: the hard-output detection and soft-output detection. Requiring higher computational complexity, the soft-output detector can provide bit likelihood ratios (LLRs) to the subsequent channel decoder to recover coded bits with lower error probability. In this thesis, we apply the LORD (Layered ORthogonal lattice Detector) algorithm to detect the 64-QAM modulated signals transmitted over the 4-by-4 space division multiplexing (SDM) MIMO system. The first step of the LORD detector is to compute the QR-decomposition (QRD) of multiple permuted channel matrices. To facilitate timing control due to matrix permutation, we insert a null signal (e.g., signal 0) between the input channel matrix and the identity matrix. The QRD output Q- and R-matrix pairs are permuted and are triangulated to generate the desired QRD matrix pairs. Next, Orthogonal Real Value Decomposition (ORVD) are used to convert the complex-valued signal model to the real-valued signal model. For the tree search, we use our proposed lookup table (LUT) modified fixed sphere decoder (FSD) algorithm. In our algorithm, we use LUT to for the root node to span child nodes at the top two layers. The nodes on other layers span only one child nodes. Also, the maximum likelihood (ML) enhancement technique is used to improve the quality of our bit LLR calculation. Under the TSMC 90nm CMOS process environment, we synthesize our design by the Synopsys Design Compiler, and, place-and-route by the Cadence SOC Encounter. While operating at frequency 250MHz, our design can reach detection throughput rate at 1 Gbps.
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