考量延遲變異在高能效 深層網路設計實現之研究;Study of Delay Variations in Energy-Efficient DNN Designs

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Title:	考量延遲變異在高能效深層網路設計實現之研究;Study of Delay Variations in Energy-Efficient DNN Designs
Authors:	胡至謙;Hu, Chih-Chien
Contributors:	資訊工程研究所
Keywords:	自適性電壓調控;定點數設計;深層神經網路;adaptive voltage scaling;fixed-point design;deep neural network
Date:	2018
Issue Date:	2019-05-23 10:30:07 (UTC+8)
Publisher:	資訊工程研究所
Abstract:	機器學習(Machine Learning)以被廣泛用於物聯網中的邊緣裝置(edge-device)，為了能在邊緣裝置上運作，需要設計特定的硬體架構來降低能耗。時序偵測器(timing sensor)可以偵測晶片內部的運作狀況，透過動態調整晶片的供給電壓來補償PVTD的變異，本論文以28 nm製程之cell based設計與FPGA重現ISSCC 2017哈佛大學的設計[20]，哈佛大學使用的機器學習演算法是深層神經網路（deep neural network; DNN），為了使實現硬體深層神經網路架構，本論文提出定點數的深層神經網路設計，並透過正規化的技術使運算結果不會溢位，以即提高位元數的利用率，避免深層神經網路在不同層需要整數與小數之競爭，可有效降低3bit之字長。本論文透過時序偵測量測深層神經網路在動態電壓調整(dynamic voltage scaling; DVS)FPGA上的時續錯誤與結果的精確性，發現DNN無法在低電壓下自行吸收時序錯誤(timing error)。在哈佛大學的論文中並無提到增加時序偵測器的偵測範圍(detection window)所花費的成本，本論文在28 nm製程下模擬出增加偵測範圍所花費的成本，越大的偵測範圍則需花費越多成本，可能導致結果並無更加的節省耗能。 Machine Learning (ML) techniques have been widely utilized in an edge-device of Internet of Things (IoT) devices. Achieving sufficient energy efficiency to execute ML workloads on an edge-device necessitates specialized hardware with efficient digital circuits. Timing sensor can detect internal operation of chip, it thru dynamic voltage scaling compensated PVTA variations. This paper presents the design of "A 28nm SoC with a 1.2GHz 568nJ/Prediction Sparse Deep-Neural-Network Engine with >0.1 Timing Error Rate Tolerance for IoT Applications" on Xilinx 28nm FPGA (Artix7). Harvard University used deep neural network as Machine Learning algorithm. In order to implement hardware on deep neural network architecture. This paper presents fixed-point operation on deep neural network design, it used normalized method to avoid overflow of computed result, and increased utilization rate on most significant bit, which can prevent race between integer and fraction on different layer of DNN and decreased 3-bit capacity. We used timing sensor measured timing violation and result accuracy of DNN after dynamic voltage scaling on FPGA, which unable correct timing violation in low voltage. In Harvard University's paper, which does not mention the overhead on increase detection window of timing sensor. This paper simulate the overhead while increased detection window on 28nm, hence it may not get benefit on power consumption while increased timing sensor's detection window.
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