National Chung Cheng University Institutional Repository:Item A095B0000Q/393
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    题名: 使用電壓掃描法應用於小型光伏面板之全域最大功率追蹤系統;A Design of Global Maximum Power Point Tracking Systems for Small Photovoltaic Panels Using Voltage Sweep
    作者: 宋奇穎;SUNG, CHI-YING
    贡献者: 電機工程研究所
    关键词: 電壓掃描法;小型光伏面板;部分遮蔽情形;全域最大功率追蹤;voltage sweep method;small photovoltaic panels;partially shaded conditions;global maximum power point tracking
    日期: 2017
    上传时间: 2019-07-17
    出版者: 電機工程研究所
    摘要: 本篇論文完成一使用電壓掃描法應用於小型光伏面板之全域最大功率追蹤(Global Maximum Power Point Tracking, GMPPT)系統。雖然在周遭環境中,光能普遍存在且可以產生大量的能量,可是當太陽能板(Solar Panels, SPs)上發生部分遮蔽情形(Partially Shaded Conditions, PSC)時,會使最佳工作點產生飄移並使得功率-電壓電氣曲線呈現多個峰值的現象,導致提取的能量減少。因此,需求一個全域最大功率追蹤系統來追蹤多峰值中所對應的最佳工作點電壓,用以提高能量提取的效率。本論文所採用的全域最大功率點演算法是基於電壓掃描法。利用一功率級電晶體與運算放大器組成一個負回授迴路,只要給定參考電壓,便可以將Vpv穩在參考電壓值,接著透過步階方式來增加電壓便可以得到Vpv資訊,功率級電晶體上流過的電流為Ipv資訊,有此兩者資訊並利用電路實現演算法便可以得到最大功率點電壓。為了避免取樣電容漏電效應,在此將類比資訊轉為數位碼進行運算,並透過D型正反器儲存數位碼。最終透過數位類比轉換器(Digital-to-Analog Converter, DAC)將最大功率點數位碼轉成類比電壓。追蹤至全域最大功率點的時間約為10ms,系統待機時間為10s,全域最大功率點電壓追蹤峰值效率為99.38%。最後,本實驗建構一小型並列太陽能板,透過兩塊不同規格的太陽能板並聯而成,VOC分別為2.5V與4V,尺寸分別為60×65 mm2與60×110 mm2。本論文晶片使用台灣積體電路公司0.18μm 1P6M CMOS製程,以48 S/B封裝,尺寸為2.1×1.8 mm2。
    This thesis completes a design of global maximum power point tracking systems for small photovoltaic panels using voltage sweep. Although light energy is ubiquitous and can generate large amounts of energy in the surrounding environment, however, when the partially shaded conditions occurs on solar panels, the best working point is drifted so that the P-V electrical curve presents multiple maxima, resulting in reduced energy extraction. Therefore, a global maximum power point tracking system is required to track the optimum operating point voltage corresponding to multiple maxima to improve the efficiency of energy extraction.In this thesis, the algorithm uses voltage sweep method. The use of power transistor and opamp to form a negative feedback loop, as long as a given reference voltage, Vpv can be stable to reference voltage, and then through the step to increase the voltage can get information of Vpv, current of power transistor is the information of Ipv, have both the information and use the circuit to achieve the algorithm, can get the maximum power point voltage. In order to avoid sampling capacitor leakage effect, the analog information will be converted to digital code to operate, and through the D-type flip-flop to store digital code. Finally, the digital-to-analog converter converts the digital code of maximum power point into analog voltage. The time to track to the global maximum power point is about 10ms, the system standby time is 10s, and the tracking peak efficiency of the global maximum power point voltage is 99.38%.Finally, parallelly connected solar panels with different specifications were constructed in the experiment. VOC are 2.5-V and 4-V, respectively, and the dimensions are 60×65 mm2 and 60×110 mm2, respectively. The chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm 1P6M CMOS mixed-signal polycide process. The package of chip is 48 S/B and the die area of the chip is 2.1×1.8 mm2.
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