應用於醫學超音波影像系統之寬頻連續時間三角積分調變器之架構設計與分析;Design and Analysis Wideband Continuous-Time ΔΣ Modulators for Medical Ultrasound Imaging Systems

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Title:	應用於醫學超音波影像系統之寬頻連續時間三角積分調變器之架構設計與分析;Design and Analysis Wideband Continuous-Time ΔΣ Modulators for Medical Ultrasound Imaging Systems
Authors:	鄭登全;CHENG, TENG-CHUAN
Contributors:	電機工程研究所
Keywords:	連續時間三角積分調變器;類比數位轉換器;時脈抖動;額外迴路延遲;超音波微換能器;continues-time sigma-delta modulator;analog-to-digital converter;clock jitter;excess loop delay;CMUT
Date:	2017
Issue Date:	2019-07-17
Publisher:	電機工程研究所
Abstract:	本論文設計超音波微換能器與連續時間三角積分調變器應用於高解析度的超音波影像系統。超音波系統包含超音波換能器、低雜訊放大器、濾波器、類比數位轉換器以及影像處理。超音波微換能器提出五種架構分別提升最高5.8倍的輸出以及更高的線性度。連續時間三角積分調變器分別為改善額外延遲與時脈抖動提出三種新架構。預測路徑架構將量化器的預測值送回迴路濾波器，能提供接近2倍時脈週期的額外延遲容忍時間，並且達到 SNDR 70dB。改良式推疊架構利用將減少主路徑上的額外延遲又保持迴路濾波器的積分能力，並設計零點補償改善諧振器的補償係數衰減的缺點達到SNDR 83.6dB。數位積分器回授架構利用將DAC回授改在第一級積分器輸出端，使得回授路徑也獲得一階雜訊移頻的好處，可以容忍77ps的DAC時脈抖動且保持SNDR 72dB。連續時間三角積分調變器頻寬達到44kHz到8 MHz，品質因數達到0.056 J/conv.，使用180奈米CMOS製程。 This research designs the capacitive micromachined ultrasonic transducers (CMUTs) and continuous-time sigma-delta modulators, applied to high-resolution ultrasound imaging systems. The ultrasound systems includes ultrasound transducers, low-noise amplifiers, filters, analog-to-digital converters, and image processing units. Five CMUT architectures are proposed to enhance the sensitivity by 5.8 times and higher linearity is achieved. For continuous-time sigma-delta modulators three new architectures are proposed to improve clock jitter and excess loop delay. Forecast architecture is designed to send the predictive values from the quantizer back into the loop filter. Nearly double time of the clock cycle for tolerating excess loop delay is achieved, and SNDR is 70 dB. Modified stack architecture utilizes direct connection of the first stage output to the third stage integrator and provides a compensation path to the second stage output, thereby reduces the extra delay of the primary path and keep the integration capability of the loop filter, and SNDR is 83.6 dB. Furthermore, zero compensation is designed to improve the attenuation coefficients of the resonator. Digital integrator feedback architecture utilizes the DAC feedback at the first stage integrator output. The feedback path benefits from the first-order noise shaping, which can tolerate 77 ps DAC clock jitter while maintaining SNDR of 72 dB. The continuous-time delta-sigma modulator achieves a bandwidth of 44 kHz to 8 MHz with a quality factor of 0.056 J/conv.. The chip is fabricated in 180 nm standard CMOS process.
Appears in Collections:	[電機工程研究所] 學位論文

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