English  |  正體中文  |  简体中文  |  Items with full text/Total items : 888/888 (100%)
Visitors : 13628098      Online Users : 263
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://ccur.lib.ccu.edu.tw/handle/A095B0000Q/335

    Title: 具電源網路壓降感知之高效率直流對直流降壓型電源轉換器設計;Design of Power Network IR-Drop-Aware High Efficiency DC-DC Buck Converter
    Authors: 林稚超;LIN, CHIH-CHAO
    Contributors: 電機工程研究所
    Keywords: 直流轉直流電源轉換器;電源轉換器;電源管理晶片;電源網路壓降感知;高轉換效率;Power Network IR-Drop-Aware;DC-DC Converter;Power Converter;Power Management IC;High Power Efficiency
    Date: 2016
    Issue Date: 2019-07-17
    Publisher: 電機工程研究所
    Abstract: 隨著先進製程的蓬勃發展,電壓壓降損耗在現代晶片製作中逐漸變成不可忽視的議題存在,隨著電晶體的尺寸及導線寬度變窄,電壓壓降損耗變得越來越嚴重。為了找出在電源分配網路中電壓壓降損耗最嚴重的路徑,設計者通常要從模擬結果中檢查所有可能會發生電壓壓降損耗的導通路徑,而現代多功能系統晶片的輸入端數量皆是百根腳位以上,這對設計者而言將是耗費數日才能完成的初步驗證,如果考量到多功能系統晶片中的電路區塊之動態負載變化及判定最嚴重之路徑準確度,那將會耗費許多人力與成本。因此在本論文中提出一個可應用在多功能晶片系統的具電源網路壓降感知之高效率直流對直流降壓型電源轉換器,利用混合訊號電路來改善因供應電壓在傳遞過程因傳遞路徑之等效電阻而導致電壓壓降損耗,進而讓後端電路效能穩定。此外,本架構提供額外技術,可根據多功能晶片系統的電流需求狀況進行供應排序智慧化,進而增加整體電路效能。 本論文使用台積電TSMC 0.18μm 1P6M 3.3V Mixed Signal製程製作,實驗結果顯示本論文提出的電源網路壓降感知機制能提升(所有電路區塊電壓壓降損耗總和)/N之電壓值(N=電路個數),並有效的減輕電源分配網路成本。關鍵字:電源管理晶片、電源轉換器、直流轉直流電源轉換器、電源網路壓降感知、高轉換效率
    Voltage drops are one of the most stringent problems in modern integrated circuit implementation, which is exacerbated by the decreasing transistor sizes and interconnect line widths. In order to find the worst case voltage drop that a power net of a design might suffer, the designer would have to check the voltage drops that occur from the simulation of all possible input vector pairs of a design. However, modern IC that have hundreds of inputs is difficult to simulate rapidly. It’s will waste much time and resource to finish it. Moreover, if we need to ensure accurate and consider all dynamic loading transient in blocks, it’s become more difficult. Therefore, we present a switching buck converter with technique of reducing IR-drop, which consist of mixed-signal circuit and traditional converter. We can improve performance of blocks by reducing IR-drop and make blocks stable. In this paper, the test chip is designed and fabricated with TSMC 0.18μm 1P6M 3.3V Mixed Signal process technology. Experiential results shows that this test chip can reducing (sum of all blocks IR-drop)/N (N = number of blocks) and reduce the cost of power distribution network.Key word: Power Management IC, Power Converter, DC-DC Converter, Power Network IR-Drop-Aware, High Power Efficiency
    Appears in Collections:[電機工程研究所] 學位論文

    Files in This Item:

    File Description SizeFormat

    All items in CCUR are protected by copyright, with all rights reserved.

    版權聲明 © 國立中正大學圖書館網頁內容著作權屬國立中正大學圖書館


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback