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    Please use this identifier to cite or link to this item: http://ccur.lib.ccu.edu.tw/handle/A095B0000Q/28


    Title: 支援時序猜測架構之迴圈轉換與指令排程技術;Loop Transformation and Instruction Scheduling Techniques for Timing Speculative Architecture
    Authors: 曾淯銘;TSENG, YU-MING
    Contributors: 資訊工程研究所
    Keywords: Timing Speculative Architecture;Compiler Optimization;LLVM;Timing Speculative Architecture;Compiler Optimization;LLVM
    Date: 2018
    Issue Date: 2019-05-23 10:30:13 (UTC+8)
    Publisher: 資訊工程研究所
    Abstract: 傳統的處理器會嚴格地限制工作的電壓與頻率以確保在最糟糕的條件下保持處理結果的正確,但隨著製成的進步與電晶體密度的提高,為了應對環境的變動衝擊,電壓與頻率限制的越加嚴格。時序猜測架構透過允許處理器可以產生錯誤結果並透過錯誤容忍機制偵測與修正錯誤以降低電壓與頻率的限制瓶頸,然而程式會因時序錯誤而造成執行效能的影響。 本研究可分為三大工作。第一,透過實驗平台分析程式指令的使用行為對時序錯誤的影響,以進行對時序猜測架構優化。第二,透過分析結果提出迴圈轉換以有效降低高達37%時序錯誤的產生。第三,透過分析結果提出指令排程技術以分散時序錯誤的分布,以增進時序猜測架構與自適應電壓縮放技術的協作與降低高達45%時序錯誤的產生。本研究將研究成果實作於開源的LLVM編譯器基礎設施上,並能夠自動地使用我們的迴圈轉換與指令排程技術產生程式。
    Traditional processor design incorporates voltage and frequency guardbands to ensure correct execution of operations under worst-case conditions. As transistor density increases and manufacturing processes improve, increasingly costly guardbands are required to deal with the impacts of environmental variability. The use of timing speculation can relax the tight constraint for worst-case design by allowing occasional errors, which are detected and corrected later by an error resilience mechanism. However, a program's performance may suffer owing to timing errors. The thesis consists of three works. First, we analyze program behaviors and observe what influence the number of timing errors through a simulator. Second, we propose a loop transformation technique for Timing Speculative Architectures to reduce up to 37% the number of timing errors. Third, we propose an instruction scheduling technique to rearrange the instructions in the programs that make better cooperation between Timing Speculative Architecture and Adaptive Voltage Scaling technique and reduce up to 45% the number of timing errors. These proposed techniques are implemented in the LLVM compiler infrastructure to generate the optimized programs automatically.
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